The present disclosure relates generally to capacitor structures, and more particularly, to capacitor structures having pairs of matched capacitors.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Several electronic devices include electronic circuits that employ capacitors for energy storage, resonant and tuning circuits, impedance matching, filtering, and other purposes. Compact design for these circuits may be achieved by using certain ceramic capacitors that may have high capacitance density due to using dielectric with particularly high permittivity. Examples of such capacitors may include class 2 multilayer ceramic capacitors (MLCC). However, high capacitance-density materials may led to devices that suffer from lack of accuracy and/or stability. For example, class 2 capacitors may have large specified tolerance margins, may suffer from large variations in the capacitance value due to temperature changes, may present voltage derating (i.e., capacitance degradation upon increase direct current (DC) voltage), and may suffer piezoelectric vibrations.
Electrical circuits that employ multiple capacitors with identical nominal specifications (i.e., matched capacitors), may be particularly vulnerable to problems arising from high capacitance density device, as the performance of the circuit may be related to how well matched the two components are. Lack of accuracy and stability in these ceramic capacitors result in other capacitors being preferred, which results in larger, non-compact electrical circuits.